HMS87C1304A Datasheet, PDF (59/70 Pages) Hynix Semiconductor – CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
17.3 Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the
on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in this mode. The on-chip RAM and
Control registers are held. The port pins out the values held
by their respective port data register, port direction regis-
ters.
The Internal RC-Oscillated Watchdog Timer mode is
activated by execution of STOP instruction after set-
ting the bit WAKEUP and RCWDT of CKCTLR to
“01”. (This register should be written by byte opera-
tion. If this register is set by bit manipulation instruc-
tion, for example “set1” or “clr1” instruction, it may be
undesired operation)
fines all the Control registers but does not change the on-
chip RAM. External interrupts allow both on-chip RAM
and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. In
this case, if the bit WDTON of CKCTLR is set to “0” and
the bit WDTE of IENH is set to “1”, the device will exe-
cute the watchdog timer interrupt service routine.() How-
ever, if the bit WDTON of CKCTLR is set to “1”, the
device will generate the internal RESET signal and exe-
cute the reset processing. ()
If I-flag = 0, the chip will resume execution starting with
the instruction following the STOP instruction. It will not
vector to interrupt service routine (refer to ).
Note: After STOP instruction, at least two or more NOP in-
When exit from Internal RC-Oscillated Watchdog Timer
struction should be written
mode by external interrupt, the oscillation stabilization
Ex) LDM WDTR,#1111_1111B
LDM CKCTLR,#0010_1110B
y _{LDM IRQH,#0}
r _{LDM IRQL,#0}
STOP
a _NOP
in ^NOP
Release the Internal RC-Oscillated Watchdog Timer mode
lim ^{The exit from Internal RC-Oscillated Watchdog Timer}
mode is hardware reset or external interrupt. Reset re-de-
time is required for normal operation. shows the timing di-
agram. When release the Internal RC-Oscillated Watchdog
Timer mode, the basic interval timer is activated on wake-
up. It is increased from 00_H until FF_H. The count overflow
is set to start normal operation. Therefore, before STOP in-
struction, user must be set its relevant prescaler divide ratio
to have long enough time (more than 20msec). This guar-
antees that oscillator has started and stabilized.
By reset, exit from internal RC-Oscillated Watchdog Tim-
er mode is shown in .
re _Oscillator
P ^{(XIN pin)}
Internal
RC Clock
Internal
Clock
External
Interrupt
(or WDT Interrupt)
STOP Instruction Execution
BIT
Counter
N-2 N-1 N N+1
N+2
Normal Operation
RCWDT Mode
Clear Basic Interval Timer
00 01
FE FF 00 00
Stabilization Time
t_ST > 20mS
Normal Operation
Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt
Jan. 2001
Preliminary
59