HMS87C1304A Datasheet, PDF (56/70 Pages) Hynix Semiconductor – CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
17. Power Saving Mode
For applications where power consumption is a critical
factor, device provides three kinds of power saving func-
tions, STOP mode, Wake-up Timer mode and internal RC-
oscillated watchdog timer mode.
The power saving function is activated by execution of
STOP instruction after setting the corresponding bit
(WAKEUP, RCWDT) of CKCTLR.
Table 17-1 shows the status of each Power Saving Mode
Note: Before executing STOP instruction, clear all in-
terrupt request flag. Because if the interrupt re-
quest flag is set before STOP instruction, the MCU
runs as if it doesn’t perform STOP instruction, even
though the STOP instruction is completed. So insert
two lines to clear all interrupt request flags (IRQH,
IRQL) before STOP instruction as shown each ex-
ample.
Peripheral
STOP
Wake-up Timer
Internal RC-WDT
RAM
Retain
Retain
Retain
Control Registers
Retain
Retain
Retain
I/O Ports
Retain
Retain
Retain
CPU
Stop
Stop
Stop
Timer0
Oscillation
y _Prescaler
r _{Internal RC oscillator}
a _{Entering Condition}
CKCTLR[6,5]
in Power Saving Release
Source
Stop
Stop
Stop
Stop
00
RESET, INT0, INT1
Operation
Oscillation
÷ 2048 only
Stop
1X
RESET, INT0, INT1,
Timer0
Stop
Stop
Stop
Oscillation
01
RESET, INT0, INT1,
RC-WDT
lim _{17.1 Stop Mode}
Table 17-1 Power Saving Mode
e _{In the Stop mode, the on-chip oscillator is stopped. With}
r _{the clock frozen, all functions are stopped, but the on-chip}
P ^{RAM and Control registers are held. The port pins out the}
to ensure that V_DD is not reduced before the Stop mode is
invoked, and that V_DD is restored to its normal operating
level, before the Stop mode is terminated.
values held by their respective port data register, port di-
rection registers. Oscillator stops and the systems internal
operations are all held up.
The reset should not be activated before V_DD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
Note: After STOP instruction, at least two or more NOP
instruction should be written
• The program counter stop the address of the
instruction to be executed after the instruction
Ex) LDM CKCTLR,#0000_1110B
“STOP” which starts the STOP operating mode.
LDM IRQH,#0
LDM IRQL,#0
The Stop mode is activated by execution of STOP in-
STOP
struction after setting the bit WAKEUP and RCWDT
NOP
of CKCTLR to “00”. (This register should be written
NOP
by byte operation. If this register is set by bit manipu-
lation instruction, for example “set1” or “clr1” instruc-
In the STOP operation, the dissipation of the power asso-
tion, it may be undesired operation)
ciated with the oscillator and the internal hardware is low-
In the Stop mode of operation, V_DD can be reduced to min-
imize power consumption. Care must be taken, however,
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
56
Preliminary
Jan. 2001