HMS87C1304A Datasheet, PDF (49/70 Pages) Hynix Semiconductor – CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
15. INTERRUPTS
The HMS87C1304A and HMS87C1302A interrupt cir-
cuits consist of Interrupt enable register (IENH, IENL), In-
terrupt request flags of IRQH, IRQL, Interrupt Edge
Selection Register (IEDS), priority circuit and Master en-
able flag(“I” flag of PSW). The configuration of interrupt
circuit is shown in Figure 15-1 and Interrupt priority is
shown in Table 15-1 .
The External Interrupts INT0 and INT1 can each be transi-
tion-activated (1-to-0, 0-to-1 and both transition).
The flags that actually generate these interrupts are bit
INT0IF and INT1IF in Register IRQH. When an external
interrupt is generated, the flag that generated it is cleared
by the hardware when the service routine is vectored to
only if the interrupt was transition-activated.
The Timer 0 and Timer 1 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective tim-
er/counter register. The AD converter Interrupt is generat-
ed by ADIF which is set by finishing the analog to digital
conversion. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register
(when the bit WDTON is set to “0”). The Basic Interval
Timer Interrupt is generated by BITIF which is set by a
overflowing of the Basic Interval Timer Register(BITR).
External Int. 0
External Int. 1
IEDS
Timer 0
Timer 1
A/D Converter
WDT
BIT
Internal bus line
ary _IRQH
in ⁷
INT0IF
INT1IF ⁶
lim ^{T0IF 5}
T1IF ⁴
re _{ADIF 7}
P⁶
IENH
Interrupt Enable
Register (Higher byte)
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
Release STOP
I Flag
Interrupt Master
Enable Flag
Interrupt
Vector
To CPU
WDTIF
Address
5
BITIF
Generator
IRQL
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 15-1 Block Diagram of Interrupt Function
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in IRQH,
IRQL) except Power-on reset and software BRK interrupt.
Interrupt enable registers are shown in Figure 15-2 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is “0”, a corre-
Jan. 2001
Preliminary
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