HMS87C1304A Datasheet, PDF (50/70 Pages) Hynix Semiconductor – CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
Reset/Interrupt Symbol Priority Vector Addr.
Hardware Reset RESET
-
External Interrupt 0 INT0
1
External Interrupt 1 INT1
2
Timer 0
Timer 0
3
Timer 1
Timer 1
4
A/D Converter
A/D C
5
Watch Dog Timer WDT
6
Basic Interval Timer BIT
7
Table 15-1 Interrupt Priority
FFFE_H
FFFA_H
FFF8_H
FFF6_H
FFF4_H
FFEA_H
FFE8_H
FFE6_H
IENH
IENL
IRQH
IRQL
Interrupt Enable Register High
ADDRESS : E2H
INT0E INT1E
T0E
T1E
-
-
-
-
RESET VALUE : 0000----
Interrupt Enable Register Low
ADDRESS : E3H
y ^{ADE WDTE BITE}
-
-
-
-
-
RESET VALUE : 000-----
r _{Enables or disables the interrupt individually}
a ^{If flag is cleared, the interrupt is disabled.}
0 : Disable
in ^{1 : Enable}
Interrupt Request Register High
ADDRESS : E4H
lim ^{INT0IF INT1IF T0IF}
T1IF
-
-
-
-
RESET VALUE : 0000----
Interrupt Request Register Low
e _{ADDRESS : E5H}
Pr ^{ADIF WDTIF BITIF}
-
-
-
-
-
RESET VALUE : 000-----
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
Figure 15-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and dis-
able any further interrupt, the return address and PSW are
pushed into the stack and the PC is vectored to. Once in the
interrupt service routine the source(s) of the interrupt can
be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.
15.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to “0” by a reset or an in-
struction. Interrupt acceptance sequence requires 8 f_OSC (2
µs at f_XIN=4MHz) after the completion of the current in-
struction execution. The interrupt service task is terminat-
ed upon execution of an interrupt return instruction
50
Preliminary
Jan. 2001