HMS87C1304A Datasheet, PDF (55/70 Pages) Hynix Semiconductor – CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
16. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the mal-
function (runaway) of program due to external noise or
other causes and return the operation to the normal condi-
tion.
The watchdog timer has two types of clock source.
The 7-bit binary counter is cleared by setting WDTCL(bit7
of WDTR) and the WDTCL is cleared automatically after
1 machine cycle.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT as shown below.
The first type is an on-chip RC oscillator which does not
require any external components. This RC oscillator is sep-
arate from the external oscillator of the Xin pin. It means
that the watchdog timer will run, even if the clock on the
Xin pin of the device has been stopped, for example, by en-
tering the STOP mode.
:
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH ; enable the RC-osc WDT
WDTR,#0FFH ; set the WDT period
; enter the STOP mode
; RC-osc WDT running
The other type is a prescaled system clock.
The RC oscillation period is vary with temperature, V_DD
and process variations from part to part (approximately,
The watchdog timer consists of 7-bit binary counter and
40~120uS). The following equation shows the RC oscillat-
the watchdog timer data register. When the value of 7-bit
ed watchdog timer time-out.
binary counter is equal to the lower 7 bits of WDTR, the
interrupt request flag is generated. This can be used as
WDT interrupt or reset the CPU in accordance with the bit
y _WDTON.
ar ^{Note: Because the watchdog timer counter is enabled af-}
ter clearing Basic Interval Timer, after the bit WD-
in ^{TON set to “1”, maximum error of timer is depend on}
prescaler ratio of Basic Interval Timer.
T _{R C W D T}= C L K _{R C} ×2⁸×[W D T R .6~ 0]+ (C L K _{R C} ×2⁸)/2
where, CLK_RC = 40~120uS
In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
T_WDT = [WDTR.6~0] × Interval of BIT
lim ^{Clock Control Register}
CKCTLR
-
WAKEUP RCWDT WDTON BTCL
re -
0
X
1
X
P ^{Watchdog Timer Register}
BTS2
X
BTS1
X
BTS0
X
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
ADDRESS : EDH
WDTR
WDTCL
7-bit Watchdog Counter Register
RESET VALUE : 01111111
Bit Manipulation Not Available
WAKEUP
RCWDT
STOP
BTS[2:0]
÷8
÷ 16
3
÷ 32
fxin
÷ 64 ⁸
÷ 128
MUX
0
÷ 256
÷ 512
1
÷ 1024
Internal RC OSC
BTCL
Clear
BITR (8-bit)
WDTR (8-bit)
WDTCL WDTON
7-bit Counter
OFD
Overflow Detection
BITIF
Basic Interval Timer
Interrupt
1
CPU RESET
0
Watchdog Timer
Interrupt Request
Figure 16-1 Block Diagram of Watchdog Timer
Jan. 2001
Preliminary
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