HY57V283220T Datasheet, PDF (5/15 Pages) Hynix Semiconductor – 4 Banks x 1M x 32Bit Synchronous DRAM

HY57V283220(L)T(P) / HY5V22(L)F(P)
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
CLK
CKE
CS
RAS
CAS
WE
DQM0
DQM1
DQM2
DQM3
Row Active
Row
Pre
Decoder
Column
Active
Column
Pre
Decoder
1M ^{x32 Bank 3}
1M x32 Bank 2
1M x32 Bank 1
1M x32 Bank 0
Memory
Cell
Array
Y decoder
DQ0
DQ1
DQ30
DQ31
Bank Select
Column Add
Counter
A0
Address
A1
Register
Burst
Counter
A11
BA0
BA1
Mode Register
CAS Latency
Data Out Control ^{Pipe Line Control}
Rev. 0.9 / July 2004
5