HY57V283220T Datasheet, PDF (1/15 Pages) Hynix Semiconductor – 4 Banks x 1M x 32Bit Synchronous DRAM

HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No.
History
0.1
Defined Preliminary Specification
1) Modified FBGA Ball Configuration Typo.
2) Changed Functional Block Diagram from A10 to A11.
0.2
3) Changed VDD min from 3.0V to 3.135V.
4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.
5) Insert tAC2 Value.
6) Insdrt tRAS & CLK Value.
0.3
Defined IDD Spec.
0.4
Delited Preliminary.
0.5
Changed IDD Spec.
0.6
133MHz Speed Added
0.7
Changed FBGA Package Size from 11x13 to 8x13.
0.8
1) Changed VDD min from 3.135V to 3.0V.
2) Changed VIL min from VSSQ-0.3V to -0.3V.
0.9
Modified of size erra. (Page15)
(Equation : 13.00 ± 10 -> 13.00 ± 0.10)
Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / July 2004