HY57V283220T Datasheet, PDF (13/15 Pages) Hynix Semiconductor – 4 Banks x 1M x 32Bit Synchronous DRAM

COMMAND TRUTH TABLE
HY57V283220(L)T(P) / HY5V22(L)F(P)
Command
CKEn-1 CKEn
CS
RAS CAS
WE
DQM ADDR
A10/
AP
BA
Mode Register Set
H
No Operation
H
Bank Active
H
Read
H
Read with Autoprecharge
Write
H
Write with Autoprecharge
Precharge All Banks
H
Precharge selected Bank
Burst Stop
H
DQM
H
Auto Refresh
H
Burst-Read-Single-WRITE
H
Self Refresh¹
Entry
H
Exit
L
Entry
H
Precharge power
down
Exit
L
Clock
Suspend
Entry
H
Exit
L
X
L
L
L
L
X
OP code
H
X
X
X
X
X
X
L
H
H
H
X
L
L
H
H
X
RA
V
L
X
L
H
L
H
X
CA
V
H
L
X
L
H
L
L
X
CA
V
H
H
X
X
L
L
H
L
X
X
L
V
X
L
H
H
L
X
X
X
V
X
H
L
L
L
H
X
X
X
L
L
L
L
X
A9 Pin High
(Other Pins OP code)
L
L
L
L
H
X
H
X
X
X
X
H
X
L
H
H
H
H
X
X
X
L
X
L
H
H
H
X
H
X
X
X
H
X
L
H
H
H
H
X
X
X
L
X
L
V
V
V
X
H
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Note
3
Rev. 0.9 / July 2004
13