HY57V283220T Datasheet, PDF (4/15 Pages) Hynix Semiconductor – 4 Banks x 1M x 32Bit Synchronous DRAM

HY57V283220(L)T(P) / HY5V22(L)F(P)
Ball CONFIGURATION ( HY5V22(L)F(P) Series)
1
A
DQ26
B
DQ28
C
VSSQ
D
VSSQ
E
VDDQ
F
VSS
G
A4
H
A7
J
CLK
K
DQM1
L
VDDQ
M
VSSQ
N
VSSQ
P
DQ11
R
DQ13
2
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
3
4
5
6
7
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
Top View
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BA0
/CAS
VDD
DQ6
DQ1
VDDQ
VDD
8
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
/CS
/WE
DQ7
DQ5
DQ3
VSSQ
DQ0
9
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
/RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
Ball DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the rising edge
of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one of the states
among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.9 / July 2004
4