HY57V283220T Datasheet, PDF (3/15 Pages) Hynix Semiconductor – 4 Banks x 1M x 32Bit Synchronous DRAM

HY57V283220(L)T(P) / HY5V22(L)F(P)
PIN CONFIGURATION ( HY57V283220(L)T(P) Series)
VDD
1
DQ0
2
VDDQ
3
DQ1
4
DQ2
5
VSSQ
6
DQ3
7
DQ4
8
VDDQ
9
DQ5
10
DQ6
11
VSSQ
12
DQ7
13
NC
14
VDD
15
DQM0
16
/W E
17
/C A S
18
/R A S
19
/C S
20
A11 21
BA0
22
BA1
23
A 1 0 /A P
24
A0
25
A1
26
A2
27
DQM2
28
VDD
29
NC
30
D Q 16
31
VSSQ
32
D Q 17
33
D Q 18
34
VDDQ
35
D Q 19
36
D Q 20
37
VSSQ
38
D Q 21
39
D Q 22
40
VDDQ
41
D Q 23
42
VDD
43
86 p in T S O P II
4 0 0 m il x 8 7 5 m il
0 .5 m m p in p itc h
86
VSS
85
D Q 15
84
VSSQ
83
D Q 14
82
D Q 13
81
VDDQ
80
D Q 12
79
D Q 11
78
VSSQ
77
D Q 10
76
DQ9
75
VDDQ
74
DQ8
73
NC
72
VSS
71
DQM1
70
NC
69
NC
68
CLK
67
CKE
66
A9
65
A8
64
A7
63
A6
62
A5
61
A4
60
A3
59
DQM3
58
VSS
57
NC
56
D Q 31
55
VDDQ
54
D Q 30
53
D Q 29
52
VSSQ
51
D Q 28
50
D Q 27
49
VDDQ
48
D Q 26
47
D Q 25
46
VSSQ
45
D Q 24
44
VSS
PIN DESCRIPTION
PIN
CLK
PIN NAME
Clock
CKE
CS
BA0, BA1
Clock Enable
Chip Select
Bank Address
A0 ~ A11
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.9 / July 2004
3