HY57V283220T Datasheet, PDF (10/15 Pages) Hynix Semiconductor – 4 Banks x 1M x 32Bit Synchronous DRAM

HY57V283220(L)T(P) / HY5V22(L)F(P)
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Symbol
-5
-55
-6
-7
-H
-8
-P
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
-S
Unit
Min Max
Note
RAS cycle time
Operation
Auto Refresh
tRC
tRRC
55 - 55 - 60 - 63 - 63 - 64 - 70 - 70 - ns
55 - 55 - 60 - 63 - 63 - 64 - 70 - 70 - ns
RAS to CAS delay
tRCD
15 - 16.5 - 18 - 20 - 20 - 20 - 20 - 20 - ns
RAS active time
tRAS
38.7
100
K
38.7
100
K
42
100
K
42
100
K
42
100
K
48
100
K
50
100
K
50
100
K
ns
RAS precharge time
tRP
15 - 16.5 - 18 - 20 - 20 - 20 - 20 - 20 - ns
RAS to RAS bank active delay
tRRD
2
-
2
-
2
-
2
-
2
-
2
- 20 - 20 - CLK
CAS to CAS delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
- CLK
Write command to data-in delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
- CLK
Data-in to precharge command
tDPL
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
- CLK
Data-in to active command
tDAL
4
-
4
-
4
-
4
-
4
-
4
-
4
-
4
- CLK
DQM to data-out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
- CLK
DQM to data-in mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
- CLK
MRS to new command
tMRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
- CLK
CAS Latency = 3 tPROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
3
- CLK
Precharge to data
output Hi-Z
CAS Latency = 2 tPROZ2
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
- CLK
Power down exit time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
- CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
- CLK 1
Refresh Time
tREF
- 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.9 / July 2004
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