HY29LV800 Datasheet, PDF (5/40 Pages) Hynix Semiconductor – 8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory

CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (V_IH) causes assertion of the
signal. A ‘#’ symbol following the signal name, e.g.,
RESET#, indicates that the signal is asserted in
the Low state (V_IL). See DC specifications for V_IH
and V_IL values.
MEMORY ARRAY ORGANIZATION
The 8 Mbit Flash memory array is organized into
19 blocks called sectors (S0, S1, . . . , S18). A
sector is the smallest unit that can be erased and
that can be protected to prevent accidental or un-
authorized erasure. See the ‘Bus Operations’ and
‘Command Definitions’ sections of this document
for additional information on these functions.
In the HY29LV800, four of the sectors, which com-
prise the boot block, vary in size from 8 to 32
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 3 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 4.
Read Operation
Data is read from the HY29LV800 by using stan-
dard microprocessor read cycles while placing the
byte or word address on the device’s address in-
puts. The host system must drive the CE# and
OE# pins LOW and drive WE# high for a valid read
operation to take place. The BYTE# pin determines
whether the device outputs array data in words
(DQ[15:0]) or in bytes (DQ[7:0]).
The HY29LV800 is automatically set for reading
array data after device power-up and after a hard-
HY29LV800
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadeci-
mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
Kbytes (4 to 16 Kwords), while the remaining 15
sectors are uniformly sized at 64 Kbytes (32
Kwords). The boot block can be located at the
bottom of the address range (HY29LV800B) or at
the top of the address range (HY29LV800T).
Tables 1 and 2 define the sector addresses and
corresponding address ranges for the top and bot-
tom boot block versions of the HY29LV800.
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host reads from an address
within an erase-suspended (or erasing) sector, or
while the device is performing a byte or word pro-
gram operation, the device outputs status data
instead of array data. After completing an Auto-
matic Program or Automatic Erase algorithm within
a sector, that sector automatically returns to the
read array data mode. After completing a program-
ming operation in the Erase Suspend mode, the
system may once again read array data with the
same exception noted above.
The host must issue a hardware reset or the soft-
ware reset command to return a sector to the read
array data mode if DQ[5] goes high during a pro-
gram or erase cycle, or to return the device to the
read array data mode while it is in the Electronic
ID mode.
Rev. 1.0/Nov. 01
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