HY29LV800 Datasheet, PDF (2/40 Pages) Hynix Semiconductor – 8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory

HY29LV800
GENERAL DESCRIPTION
The HY29LV800 is an 8 Mbit, 3 volt-only, CMOS
Flash memory organized as 1,048,576 (1M) bytes
or 524,288 (512K) words that is available in 44-
pin PSOP, 48-pin TSOP and 48-ball FBGA pack-
ages. Word-wide data (x16) appears on DQ[15:0]
and byte-wide (x8) data appears on DQ[7:0].
The HY29LV800 can be programmed and erased
in-system with a single 3 volt V_CC supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a higher voltage V_PP
power supply to perform those functions. The de-
vice can also be programmed in standard EPROM
programmers. Access times as low as 70 ns over
the full operating voltage range of 2.7 - 3.6 volts
are offered for timing compatibility with the zero
wait state requirements of high speed micropro-
cessors. A 55 ns version operating from 3.0 to
3.6 volts is also available. To eliminate bus con-
tention, the HY29LV800 has separate chip enable
(CE#), write enable (WE#) and output enable
(OE#) controls.
The device is compatible with the JEDEC single-
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings. They are
then routed to an internal state-machine that con-
trols the erase and programming circuits. Device
programming is performed a byte/word at a time
by executing the four-cycle Program Command
write sequence. This initiates an internal algorithm
that automatically times the program pulse widths
and verifies proper cell margin. Faster program-
ming times can be achieved by placing the
HY29LV800 in the Unlock Bypass mode, which
requires only two write cycles to program data in-
stead of four.
The HY29LV800’s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command sequence. This
initiates an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
As during programming cycles, the device auto-
matically times the erase pulse widths and veri-
fies proper cell margin. Hardware Sector Protec-
tion optionally disables both program and erase
operations in any combination of the sectors of
the memory array, while Temporary Sector Unpro-
tect allows in-system erasure and code changes
in previously protected sectors. Erase Suspend
enables the user to put erase on hold for any pe-
riod of time to read data from, or program data to,
any sector that is not selected for erasure. True
background erase can thus be achieved. The de-
vice is fully erased when shipped from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (toggle) status bits.
Hardware data protection measures include a low
V_CC detector that automatically inhibits write op-
erations during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another com-
mand. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Two power-saving features are embodied in the
HY29LV800. When addresses have been stable
for a specified amount of time, the device enters
the automatic sleep mode. The host can also place
the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
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Rev. 1.0/Nov. 01