HY29LV800 Datasheet, PDF (19/40 Pages) Hynix Semiconductor – 8 Mbit (1M x 8/512K x 16) Low Voltage Flash Memory

HY29LV800
START
Read DQ[7:0]
at Valid Address (Note 1)
Read DQ[7:0]
at Valid Address (Note 1)
DQ[5] = 1?
NO
YES
Read DQ[7:0]
at Valid Address (Note 1)
Read DQ[7:0]
Read DQ[7:0]
NO
(Note 4)
YES
DQ[6] Toggled?
NO
(Note 3)
PROGRAM/ERASE
COMPLETE
NO DQ[6] Toggled?
(Note 2)
YES
PROGRAM/ERASE
EXCEEDED TIME ERROR
NO
DQ[2] Toggled?
YES
SECTOR BEING READ
IS IN ERASE SUSPEND
SECTOR BEING READ
IS NOT IN ERASE SUSPEND
Notes:
1. During programming, the program address.
During sector erase, an address within any sector scheduled for erasure.
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.
3. Use this path if testing for Program/Erase status.
4. Use this path to test whether sector is in Erase Suspend mode.
Figure 8. Toggle Bit I and II Test Algorithm
limit. This is a failure condition that indicates that
the program or erase cycle was not successfully
completed. DQ[5] status is valid only while DQ[7]
or DQ[6] indicate that the Automatic Algorithm is
in progress.
The DQ[5] failure condition will also be signaled if
the host tries to program a ‘1’ to a location that is
previously programmed to ‘0’, since only an erase
operation can change a ‘0’ to a ‘1’.
For both of these conditions, the host must issue
a Reset command to return the device to the Read
mode.
DQ[3] - Sector Erase Timer
After writing a Sector Erase command sequence,
the host may read DQ[3] to determine whether or
not an erase operation has begun. When the
sector erase time-out expires and the sector erase
operation commences, DQ[3] switches from a ‘0’
to a ‘1’. Refer to the “Sector Erase Command”
section for additional information. Note that the
sector erase timer does not apply to the Chip Erase
command.
After the initial Sector Erase command sequence
is issued, the system should read the status on
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to
ensure that the device has accepted the command
sequence, and then read DQ[3]. If DQ[3] is a ‘1’,
the internally controlled erase cycle has begun and
all further sector erase data cycles or commands
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a ‘0’, the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
Rev. 1.0/Nov. 01
19