HYMP564R72CP8-E3 Datasheet, PDF (4/26 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb C ver.

1240pin Registered DDR2 SDRAM DIMMs
PIN DESCRIPTION
Pin
Pin Description
Pin
Pin Description
CK0
Clock Input, positive line
ODT[1:0] On Die Termination Inputs
CK0
Clock input, negative line
VDDQ DQs Power Supply
CKE0~CKE1 Clock Enable Input
DQ0~DQ63 Data Input/Output
RAS
Row Address Strobe
CB0~CB7 Data check bits Input/Output
CAS
Column Address Strobe
DQS(0~8) Data strobes
WE
Write Enable
DQS(0~8) Data strobes, negative line
S0,S1 Chip Select Input
DM(0~8),
DQS(9~17)
Data Maskes/Data strobes
A0~A9,
A11~A13
Address input
DQS(9~17) Data strobes, negative line
A10/AP Address input/Autoprecharge
RFU
Reserved for Future Use
BA0,BA1 SDRAM Bank Address
NC
No Connect
SCL
Serial Presence Detect (SPD) Clock Input
TEST
Memory bus test tool
(Not Connected and Not Usable on DIMMs)
SDA
SPD Data Input/Output
VDD Core Power
SA0~SA2 _E²_{PROM Address Inputs}
VDDQ I/O Power
Par_In Parity bit for the Address and Control bus
VSS
Ground
Err_Out Parity error found on the Address
VREF Input/Output Reference
RESET Reset Enable
VDDSPD SPD Power
CB0~CB7 Data Check bit Inputs/Outputs
PIN LOCATION
Front Side
1 pin
64 pin 65 pin
120 pin
121 pin
Back Side ^{184 pin 185 pin}
240 pin
Rev. 0.2 / Sep. 2008
4