HYMP564R72CP8-E3 Datasheet, PDF (21/26 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb C ver.

1240pin Registered DDR2 SDRAM DIMMs
Parameter
Symbol
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
t_CKE
t_AOND
t_AON
ODT turn-on (Power-Down mode)
ODT turn-off delay
ODT turn-off
t_AONPD
t_AOFD
t_AOF
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Average periodic Refresh Interval
t_AOFPD
tANPD
tAXPD
tOIT
tDelay
tREFI
tREFI
DDR2-667
min
max
2
15
-
WR+tRP
-
7.5
-
7.5
tRFC + 10
200
-
2
-
2
7 - AL
- continued -
DDR2-800
min
max
Unit Note
2
tCK
15
-
ns
WR+tRP
-
tCK
7.5
-
ns
7.5
ns
tRFC + 10
ns
200
-
tCK
2
-
tCK
2
tCK
8 - AL
tCK
3
3
tCK
2
2
2
2
tCK
tAC (min)
tAC (max)
+0.7
tAC (min)
tAC (max)
+0.7
ns
tAC(min)+2
2tCK+
tAC (min)
2tCK+
tAC(max)+1
+2
tAC(max)+1
ns
2.5
2.5
2.5
2.5
tCK
tAC (min)
tAC (max)+
0.6
tAC (min)
tAC (max)
+0.6
ns
tAC (min)
+2
2.5tCK+ tAC (min) 2.5tCK+
tAC(max)+1
+2
tAC(max)+1
ns
3
3
tCK
8
8
tCK
0
12
0
12
ns
tIS + tCK +
tIH
tIS + tCK
+ tIH
ns
-
7.8
-
7.8
us 2
-
3.9
-
3.9
us 3
Note:
1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS12[4, 8]21CFP).
2. 0°C †
TCASE †
°C

°C ģ
TCASE
†
°C
Rev. 0.2 / Sep. 2008
21