HYMP564R72CP8-E3 Datasheet, PDF (18/26 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb C ver.

1240pin Registered DDR2 SDRAM DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL-tRCD-tRP)
Parameter
CAS Latency
tRCD
tRP
tRAS
tRC
DDR2-800
5-5-5
min
5
12.5
12.5
45
57.25
DDR2-667
5-5-5
min
5
15
15
45
60
DDR2-533
4-4-4
min
4
15
15
45
60
DDR2-400
Unit
3-3-3
min
5
ns
15
ns
15
ns
40
ns
55
ns
AC Timing Parameters by Speed Grade
Parameter
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
Clock High Level Width
Clock Low Level Width
Symbol
tAC
tDQSCK
tCH
tCL
DDR2-400
Min
Max
-600
+600
-500
+500
0.45
0.55
0.45
0.55
Clock Half Period
tHP
min(tCL,tCH)
-
System Clock Cycle Time
tCK
DQ and DM input setup time(differential strobe)
DQ and DM input hold time(differential strobe)
DQ and DM input setup time(single ended strobe)
DQ and DM input hold time(single ended strobe)
Control & Address input Pulse Width for each input
tDS
tDH
tDS1
tDH1
tIPW
DQ and DM input pulse width for each input
tDIPW
Data-out high-impedance window from CK, /CK
tHZ
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
First DQS latching transition to associated clock edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
5000
150
275
25
25
0.6
0.35
-
tAC min
2*tAC min
-
-
tHP - tQHS
-0.25
0.35
0.35
0.2
0.2
2
0.4
8000
-
-
-
-
-
-
tAC max
tAC max
tAC max
350
450
-
+ 0.25
-
-
-
-
-
0.6
DDR2-533
Min
Max
-500
500
-500
450
0.45
0.55
0.45
0.55
min
(tCL, tCH)
-
3750
8000
100
-
225
-
-25
-
-25
-
0.6
-
0.35
-
-
tAC min
2*tAC min
-
-
tHP - tQHS
-0.25
0.35
0.35
0.2
0.2
2
0.4
tAC max
tAC max
tAC max
300
400
-
+ 0.25
-
-
-
-
-
0.6
Unit Note
ps
ns
CK
CK
ns
ps
ps 1
ps 1
ps 1
ps 1
tCK
tCK
ps
ps
ps
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Rev. 0.2 / Sep. 2008
18