HYMP564R72CP8-E3 Datasheet, PDF (2/26 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb C ver.

FEATURES
1240pin Registered DDR2 SDRAM DIMMs
• JEDEC standard 1.8V +/- 0.1V Power Supply
• V_DDQ: 1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_1.8 interface
• 4 Bank architecture
• Posted CAS
• Programmable CAS Latency 3, 4, 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequential and interleave mode
• Average Auto Refresh Period 7.8us under T_CASE 85, 3.9us at 85 < T_CASE † 95 
• High Temperature Self-Refresh Entry enable features
• PASR (Partial Array Self- Refresh)
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA
• 133.35 x 30.00 mm form factor
• Lead-free Products are RoHS compliant
ADDRESS TABLE
Density Organization Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
512MB 64M x 72
1
64Mb x 8
9
14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
1GB
128M x 72
2
64Mb x 8
18
14(A0~A13)/2(BA0~BA1)/10(A0~A9) 8K / 64ms
1GB
128M x 72
1
128Mb x 4
18 14(A0~A13)/2(BA0~BA1)/11(A0~A9,A11) 8K / 64ms
2GB
256M x 72
2
128Mb x 4
36 14(A0~A13)/2(BA0~BA1)/11(A0~A9,A11) 8K / 64ms
Rev. 0.2 / Sep. 2008
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