HYMP564R72CP8-E3 Datasheet, PDF (20/26 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb C ver.

1240pin Registered DDR2 SDRAM DIMMs
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input setup time
(differential strobe)
DQ and DM input hold time
(differential strobe)
Control & Address input pulse width for each
input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ
signals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated
clock edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Activate to precharge command
Active to active command period for 1KB
page size products
Four Active Window for 1KB page size
products
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDS
tDH
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIS
tIH
tRPRE
tRPST
tRAS
tRRD
tFAW
DDR2-667
min
max
-450
+450
-400
+400
0.45
0.55
0.45
0.55
min(tCL,
-
tCH)
3000
8000
100
-
175
-
0.6
0.35
-
tAC min
2*tAC min
-
-
tHP - tQHS
- 0.25
0.35
0.35
0.2
0.2
2
0.4
0.35
200
275
0.9
0.4
45
7.5
-
-
tAC max
tAC max
tAC max
240
340
-
+ 0.25
-
-
-
-
-
0.6
-
-
-
1.1
0.6
70000
-
37.5
-
DDR2-800
min
max
-400
+400
-350
+350
0.45
0.55
0.45
0.55
min(tCL,
-
tCH)
2500
50
-
Unit Note
ps
ps
tCK
tCK
ps
ps
ps
1
125
-
ps
1
0.6
-
tCK
0.35
-
tCK
-
tAC max ps
tAC min
tAC max ps
2*tAC min tAC max ps
-
200
ps
-
300
ps
tHP - tQHS
-
ps
- 0.25
+ 0.25
tCK
0.35
0.35
0.2
0.2
2
0.4
0.35
175
250
0.9
0.4
45
-
tCK
-
tCK
-
tCK
-
tCK
-
tCK
0.6
tCK
-
tCK
-
ps
-
ps
1.1
tCK
0.6
tCK
70000
ns
7.5
-
ns
35
-
ns
Rev. 0.2 / Sep. 2008
20