HY5S5B2BLF-6E Datasheet, PDF (39/54 Pages) Hynix Semiconductor – 256M (8Mx32bit) Mobile SDRAM

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256Mbit (8Mx32bit) Mobile SDR Memory
HY5S5B2BLF(P) Series
WRITE to PRECHARGE
Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto
Precharge was not activated). When the precharge command is executed for the same bank as the write command
that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is
unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL. To follow a
WRITE without truncating the WRITE burst, tDPL should be met as shown in Fig.
CLK
Command
WRITE
PRE
Address
BA, Col
b
DQ
DIb0 DIb1 _DIOb2 DIb3
CL = 2 or 3 BL = 4
tDPL
Non-Interrupting Write to Precharge
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.
Note that only data-inthat are registered prior to the tDPL period are written to the internal array, and any subsequent
data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent com-
mand to the same bank cannot be issued until tRP is met.
CLK
Command
WRITE
PRE
Address
DQ
BA, Col
b
DIb0 DIb1 _DIOb2
tDPL
CL = 2 or 3 BL = 4
Interrupting Write to Precharge
Rev 1.0 / Apr. 2006
39