HY5S5B2BLF-6E Datasheet, PDF (13/54 Pages) Hynix Semiconductor – 256M (8Mx32bit) Mobile SDRAM

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256Mbit (8Mx32bit) Mobile SDR Memory
HY5S5B2BLF(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System Clock
Cycle Time
CAS Latency=3
6
H
S
Symbol
Unit Note
Min Max Min Max Min Max
tCK3
6.0 1000 7.5 1000 9.5 1000 ns
Clock High Pulse Width
Clock Low Pulse Width
Access Time From Clock CAS Latency=3
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in
High-Z Time
CAS Latency=3
tCHW
tCLW
tAC3
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
2.0 -
2.5 -
3.0 -
ns
1
2.0 -
2.5 -
3.0 -
ns
1
- 5.4 - 6.5 - 7.0 ns 2
2.0 -
2.0 -
2.0 -
ns
2.0 -
2.0 -
2.0 -
ns
1
1.0 -
1.0 -
1.0 -
ns
1
2.0 -
2.0 -
2.0 -
ns
1
1.0 -
1.0 -
1.0 -
ns
1
2.0 -
2.0 -
2.0 -
ns
1
1.0 -
1.0 -
1.0 -
ns
1
2.0 -
2.0 -
2.0 -
ns
1
1.0 -
1.0 -
1.0 -
ns
1
1.0 -
1.0 -
1.0 -
ns
5.4
6.5
7.0 ns
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev 1.0 / Apr. 2006
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