HY5S5B2BLF-6E Datasheet, PDF (22/54 Pages) Hynix Semiconductor – 256M (8Mx32bit) Mobile SDRAM

11
256Mbit (8Mx32bit) Mobile SDR Memory
HY5S5B2BLF(P) Series
CURRENT STATE TRUTH TABLE (Sheet 4 of 4)
Current
State
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
Write
Recovering
H
X
X
X
X
X
LL L L
OP CODE
LL L H X
X
L L H L BA
X
Write
L L H H BA
Row Add.
Recovering
with Auto ^{L H L L BA Col Add. A10}
Precharge _{L H L H BA Col Add. A10}
LHH H X
X
HX X X
LL L L
LL L H
LLH L
LLHH
Refreshing ^{L H L L}
LH L H
LHH H
X
X
OP CODE
X
X
BA
X
BA
Row Add.
BA Col Add. A10
BA Col Add. A10
X
X
HX X X
LL L L
LL L H
LLH L
Mode
Register
LLHH
LH L L
Accessing _{L H L H}
LHH H
X
X
OP CODE
X
X
BA
X
BA
Row Add.
BA Col Add. A10
BA Col Add. A10
X
X
HX X X
X
X
Description
Action
Device Deselect
No Operation:
Row Active after tDPL
Mode Register Set ILLEGAL
Auto or Self Refresh ILLEGAL
Precharge
ILLEGAL
Bank Activate
ILLEGAL
Write/WriteAP
ILLEGAL
Read/ReadAP
ILLEGAL
No Operation
No Operation:
Precharge after tDPL
Device Deselect
No Operation:
Precharge after tDPL
Mode Register Set ILLEGAL
Auto or Self Refresh ILLEGAL
Precharge
ILLEGAL
Bank Activate
ILLEGAL
Write/WriteAP
ILLEGAL
Read/ReadAP
ILLEGAL
No Operation
No Operation:
idle after tRC
Device Deselect
No Operation:
idle after tRC
Mode Register Set ILLEGAL
Auto or Self Refresh ILLEGAL
Precharge
ILLEGAL
Bank Activate
ILLEGAL
Write/WriteAP
ILLEGAL
Read/ReadAP
ILLEGAL
No Operation
No Operation:
idle after 2 clock cycles
Device Deselect
No Operation:
idle after 2 clock cycles
Notes
13,14
13
4,13
4,12
4,12
4,9,12
13,14
13
13
13
13
13
13,14
13
13
13
13
13
Rev 1.0 / Apr. 2006
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