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HMT41GU6MFR8A Datasheet, PDF (36/57 Pages) Hynix Semiconductor – DDR3L SDRAM Unbuffered DIMMs Based on 4Gb M-Die
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DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 38.
Speed Bin
CL - nRCD - nRP
Parameter
Symbol
Internal read command
to first data
tAA
ACT to internal read or
write delay time
tRCD
PRE command period tRP
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
CWL = 5
CL = 6 CWL = 6
CWL = 7
CWL = 5
tRAS
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CL = 7
CL = 8
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CL = 9 CWL = 7 tCK(AVG)
CWL = 8 tCK(AVG)
CWL = 5, 6 tCK(AVG)
CL = 10 CWL = 7
CWL = 8
tCK(AVG)
tCK(AVG)
CL = 11
CWL = 5, 6,7
CWL = 8
tCK(AVG)
tCK(AVG)
Supported CL Settings
Supported CWL Settings
min
13.75
(13.125)5,10
13.75
(13.125)5,10
13.75
(13.125)5,10
48.75
(48.125)5,10
DDR3-1600K
11-11-11
max
20
—
—
—
35
9 * tREFI
2.5
1.875
1.875
1.5
1.5
1.25
3.3
Reserved
Reserved
Reserved
< 2.5
(Optional)5,10
Reserved
Reserved
Reserved
< 2.5
Reserved
Reserved
Reserved
<1.875
(Optional)5,10
Reserved
Reserved
<1.875
Reserved
Reserved
<1.5
5, 6, 7, 8, 9, 10, 11
5, 6, 7, 8
Rev. 1.2 / Jul. 2013
Unit
Note
ns
ns
ns
ns
ns
ns
1, 2, 3, 8
ns
1, 2, 3, 4, 8
ns
4
ns
4
ns
1, 2, 3, 4, 8
ns
1, 2, 3, 4, 8
ns
4
ns
4
ns
1, 2, 3, 8
ns
1, 2, 3, 4, 8
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 4, 8
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 8
ns
1,2,3,4
ns
4
ns
1, 2, 3
nCK
nCK
36
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