HMT41GU6MFR8A Datasheet, PDF (27/57 Pages) Hynix Semiconductor – DDR3L SDRAM Unbuffered DIMMs Based on 4Gb M-Die

Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between V_OL(AC) and V_OH(AC) for single ended signals are shown in table and Figure below.
Single-ended Output slew Rate Definition
Description
Measured
From
To
Defined by
Single-ended output slew rate for rising edge
Single-ended output slew rate for falling edge
Notes:
V_OL(AC)
V_OH(AC)
V_OH(AC)
V_OL(AC)
[V_OH(AC)-V_OL(AC)] / DeltaTRse
[V_OH(AC)-V_OL(AC)] / DeltaTFse
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse
VOH(AC)
V∏
Delta TFse
VOl(AC)
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
Parameter
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866
Units
Symbol Min Max Min Max Min Max Min Max Min Max
Single-ended Output Slew Rate SRQse 2.5 5 2.5 5 2.5 5 2.5 5 2.5 ₅¹⁾ V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from
low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular
maximum limite of 5 V/ns applies.
Rev. 1.2 / Jul. 2013
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