HY5DU56422DTP Datasheet, PDF (32/37 Pages) Hynix Semiconductor – 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)

HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR266A
Min
Max
DDR266B
Min
Max
DDR200
Min
Max
Row Cycle Time
tRC
65
-
65
-
70
-
Auto Refresh Row Cycle Time
tRFC
75
-
75
-
80
-
Row Active Time
tRAS
45
120K
45
120K
50
120K
Active to Read with Auto Precharge Delay
tRAP
tRCD or
tRPmin
-
tRCD or
tRPmin
-
tRCD or
tRPmin
-
Row Address to Column Address Delay
tRCD
20
-
20
-
20
-
Row Active to Row Active Delay
tRRD
15
-
15
-
15
-
Column Address to Column Address Delay tCCD
1
-
1
-
1
-
Row Precharge Time
tRP
20
-
20
-
20
-
Write Recovery Time
tWR
15
-
15
-
15
-
Write to Read Command Delay
tWTR
1
-
1
-
1
-
Auto Precharge Write Recovery +
Precharge Time
(tWR/tCK)
(tWR/tCK)
(tWR/tCK)
tDAL
+
-
+
-
+
-
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
CL = 2.5
7.5
12
7.5
12
8.0
12
System Clock Cycle Time
tCK
CL = 2
7.5
12
10
12
10
12
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
Data-Out edge to Clock edge Skew
tAC
-0.75
0.75
-0.75
0.75
-0.75
0.75
DQS-Out edge to Clock edge Skew
tDQSCK -0.75
0.75
-0.75
0.75
-0.75
0.75
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.5
-
0.5
-
0.6
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
Data Hold Skew Factor
tQHS
-
0.75
-
0.75
-
0.75
Valid Data Output Window
tDV
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
Data-out high-impedance window from
CK,/CK
tHZ
-0.75
0.75
-0.75
0.75
-0.8
0.8
Data-out low-impedance window from
CK, /CK
tLZ
-0.75
0.75
-0.75
0.75
-0.8
0.8
Unit Note
ns
ns
ns
ns 16
ns
ns
CK
ns
ns
CK
CK 15
ns
ns
CK
CK
ns
ns
ns
ns 1,10
ns 1,9
ns 10
ns
ns 17
ns 17
Rev. 0.1 /May 2004
32