HY5DU56422DTP Datasheet, PDF (2/37 Pages) Hynix Semiconductor – 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)

DESCRIPTION
HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
PRELIMINARY
The Hynix HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622(L)TP are a 268,435,456-bit CMOS Double
Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• VDD, VDDQ = 2.5V +/- 0.2V
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
• Programmable CAS latency 1.5, 2, 2.5 and 3
supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed
/RAS
• tRAS Lock-out function supported
• Auto refresh and Self refresh supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch (Lead free package)
• Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
OPERATING FREQUENCY
Part No.
HY5DU56422D(L)TP-X*
HY5DU56822D(L)TP-X*
HY5DU561622D(L)TP-X*
Configuratio
n
64Mx4
32Mx8
16Mx16
Package
400mil
66pin
TSOP-II
(Lead-
free)
* X means speed grade
Grade
-J
-M
-K
-H
-L
CL2
133MHz
133MHz
133MHz
100MHz
100MHz
CL2.5
166MHz
133MHz
133MHz
133MHz
125MHz
Remark
(CL-tRCD-tRP)
DDR333 (2.5-3-3)
DDR266 (2-2-2)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR200 (2-2-2)
* CL1.5 @ DDR200 supported
* CL3 supported
Rev. 0.2 / July 2003
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