HMT451R7MFR8A Datasheet, PDF (24/71 Pages) Hynix Semiconductor – DDR3L SDRAM Registered DIMM Based on 4Gb M-die

32GB, 4Gx72 Module(4Rank of x4) - page5
S0
1:2
R
S1
E
G
I
S
BA[N:0]
T
A[N:0]
E
RAS
R
/
CAS
P
L
WE
L
CKE0
A
CKE1
ODT0
CK0
120 Ω
±5%
CK0
ARS0A → CS1: SDRAMs D1,D3,D5,D7 D9,
S2
D19, D21, D23, D25, D27
1:2
ARS0B → CS1: SDRAMs D11, D13, D15, D17,
D29, D31, D33, D35
R
ARS1A → CS0: SDRAMs D0, D2, D4, D6, D8,
S3
D18, D20, D22, D24, D26
E
G
ARS1B → CS0: SDRAMs D10, D12, D14, D16,
I
D28, D30, D32, D34
S
AARRBBAA[[NN::00]]BA
→
→
BA[N:0]:
BA[N:0]:
SDRAMs
SDRAMs
D[9:0],D[27:18]
D[17:10],D[35:28]
BA[N:0]
T
AARRAA[[NN::00]]AB
→
→
A[N:0]:
A[N:0]:
SDRAMs
SDRAMs
D[9:0],D[27:18]
D[17:10],D[35:28]
ARRASA → RAS: SDRAMs D[9:0],D[27:18]
ARRASB → RAS: SDRAMs D[17:10],D[35:28]
A[N:0]
RAS
E
R
/
ARCASA → CAS: SDRAMs D[9:0],D[27:18]
ARCASB → CAS: SDRAMs D[17:10],D[35:28]
CAS
P
L
ARWEA → WE: SDRAMs D[9:0],D[27:18]
ARWEB → WE: SDRAMs D[17:10],D[35:28]
WE
L
ARCKE0A → CKE1: SDRAMs D1,D3,D5,D7,D9,
CKE0
B
D19, D21, D23, D25, D27
ARCKE0B → CKE1: SDRAMs D11,D13,D15,D17,
D29, D31, D33, D35
ARCKE1A → CKE0: SDRAMs D0,D2,D4,D6,D8,
CKE1
D18, D20, D22, D24, D26
ARCKE1B → CKE0: SDRAMs D10,D12,D14,D16,
D28, D30, D32, D34
ARODT0A → ODT1: SDRAMs D1,D3,D5,D7,D9, ODT1
D19, D21, D23, D25, D27
ARODT0B → ODT0: SDRAMs D11,D13,D15,D17,
D29, D31, D33, D35
APCK0A → CK: SDRAMs D[9:0]
APCK0B → CK: SDRAMs D[17:10]
APCK1A → CK: SDRAMs D[27:18]
APCK1B → CK: SDRAMs D[35:28]
APCK0A → CK: SDRAMs D[9:0]
APCK0B → CK: SDRAMs D[17:10]
APCK1A → CK: SDRAMs D[27:18]
APCK1B → CK: SDRAMs D[35:28]
CK0
120 Ω
±5%
CK0
BRS2A → CS1: SDRAMs D45,D47,D49,D51,D53
D63,D65,D67,D69,D71
BRS2B → CS1: SDRAMs D37,D39,D41,D43,
D55,D57,D59,D61
BRS3A → CS0: SDRAMs D44.D46,D48,D50,D52,
D62,D64,D66,D68,D70
BRS3B → CS0: SDRAMs D36,D38,D40,D42,
D54,D56,D58,D60
BBRRBBAA[[NN::00]]BA
→
→
BA[N:0]:
BA[N:0]:
SDRAMs
SDRAMs
D[53:44],D[71:62]
D[43:36],D[61:54]
BBRRAA[[NN::00]]BA
→
→
A[N:0]:
A[N:0]:
SDRAMs
SDRAMs
D[55:44],D[71:62]
D[43:36],D[61:54]
BRRASA → RAS: SDRAMs D[53:44],D[71:62]
BRRASB → RAS: SDRAMs D[43:36],D[61:54]
BRCASA → CAS: SDRAMs D[53:44],D[71:62]
BRCASB → CAS: SDRAMs D[43:36],D[61:54]
BRWEA → WE: SDRAMs D[53:44],D[71:62]
BRWEB → WE: SDRAMs D[43:36],D[61:54]
BRCKE0A → CKE1: SDRAMs D45,D47,D49,D51,D53,
D63,D65,D67,D69,D71
BRCKE0B → CKE1: SDRAMs D37,D39,D41,D43,
D55,D57,D59,D61
BRCKE1A → CKE0: SDRAMs D44.D46,D48,D50,D52,
D62,D64,D66,D68,D70
BRCKE1B → CKE0: SDRAMs D36,D38,D40,D42,
D54,D56,D58,D60
BRODT1A → ODT1: SDRAMs D45,D47,D49,D51,D53
D63,D65,D67,D69,D71
BRODT1B → ODT0: SDRAMs D37,D39,D41,D43
D55,D57,D59,D61
BPCK0A → CK: SDRAMs D[53:44]
BPCK0B → CK: SDRAMs D[43:36]
BPCK1A → CK: SDRAMs D[71:62]
BPCK1B → CK: SDRAMs D[61:54]
BPCK0A → CK: SDRAMs D[53:44]
BPCK0B → CK: SDRAMs D[43:36]
BPCK1A → CK: SDRAMs D[71:62]
BPCK1B → CK: SDRAMs D[61:54]
PAR_IN
Err_Out
RESET RST
RST: SDRAMs D[35:0]
PAR_IN
Err_Out
RESET RST
CK1
120 Ω
CK1
±5%
1. CK0 and CK0 are differentially terminated with a single 120 Ohms ±5% resistor.
2. CK1 and CK1 are differentially terminated with a single 120 Ohms ±5% resistor, but is not used.
3. Unused register inputs ODT1 for Register A and ODT0 for Register B are tied to ground.
4. The module drawing on this page is not drawn to scale.
Rev. 1.0 / Aug. 2013
24