HMT451R7MFR8A Datasheet, PDF (10/71 Pages) Hynix Semiconductor – DDR3L SDRAM Registered DIMM Based on 4Gb M-die

Registering Clock Driver Specifications
Capacitance Values
Symbol
Parameter
Input capacitance, Data inputs
C_I
Input capacitance, CK, CK, FBIN, FBIN
(up to DDR3-1600)
C_IR
Input capacitance, RESET, MIRROR,
QCSEN
Conditions
Min Typ Max Unit
1.5 - 2.5 pF
1.5 - 2.5 pF
V_I = V_DD or GND; V_DD = 1.5v -
-
3
pF
Input & Output Timing Requirements
Symbol Parameter
Conditions
DDR3L-800
1066/1333
Min
Max
f_clock
Input clock fre- Application fre-
quency
quency
300
670
f_TEST
Input clock fre-
quency
Test frequency
70
300
t_SU
Setup time
Input valid before
CK/CK
100
-
t_H
Hold time
Input to remain
valid after CK/CK
175
-
Propagation
t_PDM delay, single-bit CK/CK to output
0.65
1.0
switching
t_DIS
Output disable
time (1/2-Clock
prelaunch)
Yn/Yn to output
float
0.5 + tQSK1(min)
-
t_EN
Output enable
time (1/2-Clock
prelaunch)
Output driving to
Yn/Yn
0.5 -
tQSK1(max)
-
DDR3L-1600
Min
Max
300
810
70
300
50
-
125
-
0.65
1.0
0.5 + tQSK1(min)
-
0.5 - tQSK1(max)
-
Unit
Mhz
Mhz
ps
ps
ns
ps
ps
Rev. 1.0 / Aug. 2013
10