HMT451R7MFR8A Datasheet, PDF (19/71 Pages) Hynix Semiconductor – DDR3L SDRAM Registered DIMM Based on 4Gb M-die

16GB, 2Gx72 Module(2Rank of x4) - page3
S0
1:2
S1
R
BA[N:0]
E
A[N:0]
G
RAS
I
S
CAS
T
E
WE
R
CKE0
/
P
CKE1
L
ODT0
L
ODT1
CK0
CK0
CK1
120 Ω
CK1
±5%
PAR_IN
RESET RST
RS0A → CS0: SDRAMs D[3:0], D[12:8], D17
RS0B → CS0: SDRAMs D[7:4], D[16:13]
RS1A → CS1: SDRAMs D[21:18], D[30:26], D35
RS1B → CS1: SDRAMs D[25:22], D[34:31]
RRBBAA[[NN::00]]BA
→ BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
→ BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RRAA[[NN::00]]AB
→ A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
→ A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RRASA → RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASB → RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCASB → CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RWEA → WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RWEB → WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B → CKE0: SDRAMs D[7:4], D[16:13]
RCKE1A → CKE1: SDRAMs D[21:18], D[30:26], D35
RCKE1B → CKE1: SDRAMs D[25:22], D[34:31]
RODT0A → ODT0: SDRAMs D[3:0], D[12:8], D17
RODT0B → ODT0: SDRAMs D[7:4], D[16:13]
RODT1A → ODT1: SDRAMs D[21:18], D[30:26], D35
RODT1A → ODT1: SDRAMs D[25:22], D[34:31]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
Err_Out
RST: SDRAMs D[35:0]
* S[3:2], CK1 and CK1 are NC
Rev. 1.0 / Aug. 2013
19