H1A424M167 Datasheet, PDF (24/47 Pages) Hynix Semiconductor – Image Signal Processor for Hyundai CMOS Image Sensor

Hyundai Electronics Industries Co., Ltd.
H1A424M167
8.2. BASE Register Map
( MCU Address Space 80h~95h )
8.2.1. Normal Register[80h~83h]
Operating Mode Register[80h]
[02h]
[7]
[6]
[5]
[4]
[2]
[1]
[0]
[ 7..6 ] Sensor PCLK divider
0 : MCLK/3, 1: MCLK/6, 2: MCLK/12, 3: MCLK/24
* Note : Normally, use MCLK/3 with VGA(HV7131X), CIF(HV7121X) CIS
[R/W]
[ 5..4 ] ISP Clock divider
[R/W]
0 : MCLK/3, 1: MCLK/6, 2: MCLK/12, 3: MCLK/24
* Note : Normally, use MCLK/3 with VGA(HV7131X) CIS, MCLK/6 with CIF(HV7121X)
CIS
[ 2..0 ]
Operating Mode Set
[R/W]
1 0 0 : VGA ( 1 to 1 Mode )
0 1 1 : C I F ( Subsample Mode )
0 1 0 : S I F ( Subsample Mode )
0 0 1 : QCIF ( Subsample Mode )
0 0 0 : QSIF ( Subsample Mode )
These bits specifies which one of color interpolation methods is used,
VGA
: color interpolation using 3x3 spatial kernel
CIF/SIF
: color interpolation using 3/4 subsampling using 2x2 kernel
QCIF/QSIF : color interpolation using 3/16 subsampling using 4x4 kernel
and also specifies which one of input image size scalings is used.
VGA
: 1/1 scaling
CIF/SIF
: 1/4 scaling
QCIF/QSIF : 1/16 scaling
a) Subsampling mode definitions
3/4 subsampling : 2x2 Bayer Data for four sensor pixels.
ð R/G/B Data for a output pixel in CIF/SIF mode.
Subsampling window moves by 2 pixels in horizontal
and vertical directions.
3/16 subsampling: 4x4 Bayer Data for sixteen sensor pixels.
ð R/G/B Data for a output pixel in QCIF/QSIF mode.
Subsampling window moves by 4 pixels in horizontal
and vertical directions.
b) In VGA(1 to 1 Mode) mode operation, ISP needs the input image with 642 X
482 size for horizontal and vertical interpolation. In CIF,SIF,QCIF,QSIF
(Subsample Mode) mode operation, ISP needs the input image with 640 X
482 for vertical interpolation. The reason that vertical height is two lines plus
480 is that internal ISP logic requires two lines timing margin to support
CIF/QCIF/X-flip functions. For CIF mode, horizontal blank period of a sensor
must be larger than 64 pixel clock.
1999 October 11
Page 24