H1A424M167 Datasheet, PDF (15/47 Pages) Hynix Semiconductor – Image Signal Processor for Hyundai CMOS Image Sensor

Hyundai Electronics Industries Co., Ltd.
H1A424M167
CSB
ALE
IOW
IODone
AD[7:0]
Stretched
A[7:0]
D[7:0]
Stretched
Active write operation
Host Parallel Write Operation
Similar to parallel read operation, parallel write operation needs only 1 operation cycle.
The host must watch ‘IODone’ signal for a proper write operation. IODone signal
indicates the completion of read/write operation. So the host must hold the IOW, CSB,
Write Data[7:0] signals until IODone signal become active. When IODone signal
become active, ISP accept the write data internally. At the final stage, the host ends the
bus cycle(CSB, IOW, Write Data[7:0]) and IODone signal become inactive.
ISP holds IODone active until read/write operation is completed. CIS register read/write
operation needs more time than ISP register read/write operation. So IODone active
signal for CIS register read/write operation is much longer than that of ISP register
read/write operation.
7.1.3. Serial or Parallel Interface selection
The selection between serial interface and parallel interface is made at hardware reset
time. If CSB/MODE pin, pin number 64, is pulled down during reset, Serial Interface is
configured, and otherwise parallel interface is selected.
For example, Serial Interface selection timing is as below.
RESETB
CSB/MODE
Serial Interface Selection
More than 64 MCLK
1999 October 11
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