H1A424M167 Datasheet, PDF (14/47 Pages) Hynix Semiconductor – Image Signal Processor for Hyundai CMOS Image Sensor

Hyundai Electronics Industries Co., Ltd.
H1A424M167
7.1.1.3. Data Transfer Timing on the serial Interface
SDA
SCL
1-1-77
S
89
START
CONDITION
ADDRESS
R//W
ACK
1-7
89
DATA
ACK
1-7
8
DATA
9
ACK
P
STOP
CONDITION
7.1.2. Host Parallel Interface
H1A424M167 ISP supports an external 8-bit microcontroller interface to access
H1A424M167 internal registers.
Basically, the data transfer operations(8bits) are multiplexed on the address bus.
CSB
ALE
IOR
IODone
Stretched
AD[7:0]
A[7:0]
D[7:0] Valid D[7:0]
Host Parallel Read Operation
A Parallel read operation always needs only 1 read cycle different from the serial read
operation. But the host must watch ‘IODone’ signal for a proper read operation. IODone
signal indicates the completion of read/write operation. So the host must hold the IOR,
CSB signals until IODone signal is active, to read the valid data on AD[7:0] lines. At the
final stage, the host ends the bus cycle(CSB, IOR) then IODone signal become
inactive.
1999 October 11
Page 14