H1A424M167 Datasheet, PDF (16/47 Pages) Hynix Semiconductor – Image Signal Processor for Hyundai CMOS Image Sensor

Hyundai Electronics Industries Co., Ltd.
H1A424M167
7.2. Clock(MCLK, PCLK, VCLK) Timing Diagram
This chart shows the timing diagram in the YCbCr 4:2:2, 16bit video mode.
MCLK
PCLK
VCLK
Y[7:0]
UV[7:0]
VCLK
Y0
Y1
Y2
Y3
Y4
Y5
U0
V0
U2
V2
U4
V4
OP_MODE (VGA)
Y[7:0]
Y0
Y1
Y2
UV[7:0]
U0
V0
U2
OP_MODE (SIF,CIF,QSIF,QCIF)
* Note : HV7131B(VGA) CMOS Sensor is used for this timing diagram.
7.3. Video Output Interface
The H1A424M167 outputs video data in YUV 4:2:2 format through the 16-bit (Y[7:0]
and UV[7:0]) data bus. Video data is changed at the rising edge of the VCLK signal. UV
order can be selected by programming OUT_FORM register. VCLK frequency is same
to PCLK frequency in VGA mode when the 16-bit video mode is enabled. VCLK
frequency is a half of PCLK frequency in SIF,CIF,QSIF,QCIF modes when the 16-bit
video mode is enabled. (See OP_MODE register description.)
Some video codec needs several HSYNC pulses within active VSYNC. So, The
H1A424M167 can modify input VSYNC width by programming HSYNC_COUNT
register for VSISP pulse to contain several HSYNC pulses.
All YUV 16bit ports are active for every HSISP lines in YUV 4:2:2, 16bit video mode.
All YUV 16bit ports are active for even HSISP lines, and only Y 8bit ports are active for
1999 October 11
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