H1A424M167 Datasheet, PDF (13/47 Pages) Hynix Semiconductor – Image Signal Processor for Hyundai CMOS Image Sensor

Hyundai Electronics Industries Co., Ltd.
H1A424M167
CMOS Image Sensor register access through the ISP chip needs two sequential read
operations to compensate the read access delay from CMOS Image Sensor to ISP.
The second read data for the CMOS image sensor register should be recognized as
the right value of the accessed register. But when the ISP auto functions are enabled,
there will be a variable delay for the right data transfer from the CMOS image sensor to
the ISP at the first read access, so the second read access may not get acknowledge
from the ISP until the first read access is completely processed in the ISP. To take care
of the said situation, a system host should repeat the second read access until it get
acknowledge from the ISP or there should be sufficient delay between two accesses.
To summarize, the ISP general register read access is always completed by only one
read transaction, and the CMOS image sensor register access needs two fully
acknowledged read transactions and the last read data is the right value for the
accessed register.
The single read access sequence is as follows.
S1 DADDR 1 A1 SADDR A2 S2 DADDR 2 A3 READ DATA A4 P
[ S1 ]
[ DADDR 1 ]
[ A1 ]
[ SADDR ]
[ A2 ]
[ S2 ]
[ DADDR 2 ]
[ A3 ]
[ READ DATA ]
[ A4 ]
[P]
Start condition
Device Address ISP 40h(010_0000 + 0),
CIS 22h(001_0001 + 0)
ð device address + R/W bit
Acknowledge from ISP
ISP Sub address space 80h ~ FFh
CIS Sub address space 00h ~ 7Fh
Acknowledge from ISP
Start condition
Device Address ISP 41h(010_0000 + 1),
CIS 23h(001_0001 + 1)
ð device address + R/W bit
Acknowledge from ISP
Register Value from ISP
Acknowledge from HOST
Stop condition
* Note ( Importance ! )
ISP General Register Read : 1 Read Operation needed.
CIS Register Read : 2 Read Operation needed, valid data at second read operation.
ISP recognize CIS read command at first read.
1999 October 11
Page 13