HYMP532S646-E3 Datasheet, PDF (18/23 Pages) Hynix Semiconductor – 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.

1200pin Unbuffered DDR2 SDRAM SO-DIMMs
- Continued -
Parameter
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Auto-Refresh to Active/Auto-Refresh command
period
Row Active to Row Active Delay for 1KB page size
Row Active to Row Active Delay for 2KB page size
Four Activate Window for 1KB page size
Four Activate Window for 2KB page size
CAS to CAS command delay
Write recovery time
Auto Precharge Write Recovery + Precharge Time
Write to Read Command Delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Average periodic Refresh Interval
Symbol
tIS
tIH
tRPRE
tRPST
DDR2-400
Min
Max
350
-
475
-
0.9
1.1
0.4
0.6
DDR2-533
Min
Max
250
-
375
-
0.9
1.1
0.4
0.6
Unit Note
ps
ps
tCK
tCK
tRFC
105
-
105
-
ns
tRRD
7.5
-
7.5
-
ns
tRRD
10
-
10
-
ns
tFAW
37.5
-
37.5
-
ns
tFAW
50
-
50
-
ns
tCCD
2
2
tCK
tWR
15
-
15
-
ns
tDAL
tWR+tRP
-
tWR+tRP
-
tCK
tWTR
10
-
7.5
-
ns
tRTP
7.5
7.5
ns
tXSNR tRFC + 10
tRFC + 10
ns
tXSRD
200
-
200
-
tCK
tXP
2
-
2
-
tCK
tXARD
2
2
tCK
tXARDS
6 - AL
6 - AL
tCK
t_CKE
3
3
tCK
t_AOND
t_AON
t_AONPD
t_AOFD
t_AOF
t_AOFPD
tANPD
tAXPD
tOIT
2
2
2
2
tCK
tAC(min)
tAC(max)+
1
tAC(min)
tAC(max)+
1
ns
tAC(min)+2
2tCK+tAC(
max)+1
tAC(min)+2
2tCK+tAC(
max)+1
ns
2.5
2.5
2.5
2.5
tCK
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+
0.6
ns
tAC(min)+2
2.5tCK+tA
C(max)+1
tAC(min)+2
2.5tCK+tA
C(max)+1
ns
3
3
tCK
8
8
tCK
0
12
0
12
ns
tDelay tIS+tCK+tIH
tIS+tCK+tIH
ns
tREFI
-
7.8
-
7.8
us 2
tREFI
-
3.9
-
3.9
us 3
Notes:
1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS12[8/16]21(L)F).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C ＜ TCASE ≤ 95°C
Rev. 1.0 / Feb. 2005
18