HYMP532S646-E3 Datasheet, PDF (1/23 Pages) Hynix Semiconductor – 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.
This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2
SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-
try standard. It is suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
• All inputs and outputs are compatible with SSTL_1.8
interface
• Posted CAS
• Programmable CAS Latency 3 ,4 ,5
• OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball(x8), 84ball(x16)
FBGA
• 67.60 x 30.00 mm form factor
• Lead-free Products are RoHS compliant
ORDERING INFORMATION
Part Name
HYMP532S646-E3/C4
HYMP564S648-E3/C4
HYMP564S646-E3/C4
HYMP112S64M8-E3/C4
HYMP532S64P6-E3/C4
HYMP564S64P8-E3/C4
HYMP564S64P6-E3/C4
HYMP112S64MP8-E3/C4
Density
256MB
512MB
512MB
1GB
256MB
512MB
512MB
1GB
Organization
32Mx64
64Mx64
64Mx64
128Mx64
32Mx64
64Mx64
64Mx64
128Mx64
# of
DRAMs
4
8
8
16
4
8
8
16
# of
ranks
1
1
2
2
1
1
2
2
Materials
Leaded
Leaded
Leaded
Leaded
Lead free
Lead free
Lead free
Lead free
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Feb. 2005
1