HYMP532S646-E3 Datasheet, PDF (16/23 Pages) Hynix Semiconductor – 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.

1200pin Unbuffered DDR2 SDRAM SO-DIMMs
IDD Meauarement Conditions
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
IDD7
Conditions
Operating one bank active-precharge current; ^tCK = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRAS} = ^tRAS-
min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
tCK ₌ tCK(IDD), tRC ₌ tRC _(IDD), tRAS ₌ tRASmin(IDD), tRCD ₌ tRCD(IDD) _{; CKE is HIGH, CS is HIGH}
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
Precharge power-down current ; All banks idle ; tCK = ^tCK(IDD) ; CKE is LOW ; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current;All banks idle; ^tCK = ^tCK(IDD);CKE is HIGH, CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current; All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current; All banks open; ^tCK = ^tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0
Other control and address bus inputs are STABLE; Data bus inputs are FLOAT-
ING
Slow PDN Exit MRS(12) = 1
Active standby current; All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; ^tCK
= ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} = ^tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = 0; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} = ^tRP(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
Burst refresh current; ^tCK = ^tCK(IDD); Refresh command at every ^tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃ max.
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = ^{tRCD(IDD)-1*tCK(IDD); tCK} = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRRD} = ^{tRRD(IDD), tRCD} = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R; - Refer to the following page for detailed timing conditions
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations
of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
Rev. 1.0 / Feb. 2005
16