HDMP-1637A Datasheet, PDF (6/16 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs

6
HDMP-1637A (Receiver Section)
Timing Characteristics
T_A = 0°C to +70°C, V_CC = 3.15 V to 3.45 V
Symbol
Parameter
f_lock
Frequency Lock at Powerup
b_sync^[1,2]
Bit Sync Time
t_{valid_before}
Time Data Valid Before Rising Edge of RBC
t_{valid_after}
Time Data Valid After Rising Edge of RBC
t_duty
t_A-B[4]
RBC Duty Cycle
Rising Edge Time Difference between
RBC0 and RBC1
t_rxlat^[3]
Receiver Latency
Units
µs
bits
nsec
nsec
%
nsec
nsec
bits
Min.
2.5
1.5
40
7.5
Typ.
Max.
500
2500
60
8.5
22.4
28.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C_PLL = 0.1 µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word
(defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
4. Guaranteed at room temperature.
t_{valid_before}
t_{valid_after}
RBC1
RX[0]-RX[9]
BYTSYNC
K28.5
DATA
DATA
DATA
DATA
1.4 V
2.0 V
0.8 V
2.0 V
0.8 V
RBC0
1.4 V
Figure 5. Receiver Section Timing.
t_A-B
DATA BYTE C
DATA BYTE D
± DIN R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
t_rxlat
RX[0]-RX[9]
DATA BYTE A
R2 R3 R4 R5
DATA BYTE D
RBC1/0
Figure 6. Receiver Latency.
1.4 V