HDMP-1637A Datasheet, PDF (14/16 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs

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V_CC
V_CC**
GND*
C_PLLR
RXCAP0
GND_RXTTL
V_CC*
V_CC_RXTTL
V_CC
HDMP-1637A
V_CC*
GND*
GND_TXA
TOP VIEW
V_CC_RXTTL
TXCAP1
C_PLLT
GND_RXTTL
V_CC
V_CC**
*IT IS RECOMMENDED THAT THESE PINS BE CONNECTED TO THE APPROPRIATE
SUPPLY LINE, EITHER V_CC OR GND, EVEN THOUGH THE PIN IS BONDED TO AN
ISOLATED PAD. REFER TO THE I/O DEFINITIONS SECTION FOR THESE PINS FOR
MORE DETAILS.
** SUPPLY VOLTAGE INTO V_CC_RXA AND V_CC_TXA SHOULD BE FROM A LOW NOISE
SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 µF.
Figure 12. Power Supply Bypass.
Startup Procedure:
The transceiver startup
procedure(s) use the following
conditions: V_CC = +3.3 V +/- 5%
and REFCLK = 125 MHz +/- 100
ppm.
After the above conditions have
been met, apply valid data using
a balanced code such as 8B/10B.
Frequency lock occurs within
500 ms. After frequency lock,
phase lock occurs within 2500
bit times.
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
Bypass capacitors should be used
and placed as close as possible to
the appropriate power supply
pins of the HDMP-1637A as
shown on the schematic of
Figure 12. All bypass chip
capacitors are 0.1 µF. The
V_CC_RXA and V_CC_TXA pins are
the analog power supply pins for
the PLL sections. The voltage
into these pins should be clean
with minimum noise. The PLL
loop filter capacitors and their
pin locations are also shown on
Figure 12. Notice that only two
capacitors are required: C_PLLT
for the transmitter and C_PLLR for
the receiver. Nominal
capacitance is 0.1 µF. The
maximum voltage across the
capacitors is on the order of 1
volt, so the capacitor can be a
low voltage type and physically
small. The PLL capacitors are
placed physically close to the
appropriate pins on the HDMP-
1637A. Keeping the lines short
will prevent them from picking
up stray noise from surrounding
lines or components.