HCPL-810J Datasheet, PDF (15/16 Pages) Agilent(Hewlett-Packard) – PLC Powerline DAA IC

Receiver
The received signal from the
powerline is often heavily
attenuated and also includes
high level out of band noise.
Receiver performance can be
improved by positioning a
suitable filter prior to the Rx- in
input (pin 10). To counter the
inevitable attenuation on the
powerline, the HCPL- 810J
receiver circuit includes a fixed
20 dB front- end gain stage. If
desired, this fixed gain can be
reduced to unity gain by
inserting an impedance of 33
kΩ in the receiver signal path.
It is however recommended to
maintain the fixed gain of 20
dB at this position and reduce
the overall signal gain elsewhere
if required. This configuration
will result in the best SNR and
IMRR.
The optical isolated Rx signal
appears at Rx- PD- out (pin 3).
This signal is subsequently AC
coupled to the final gain stage
via a capacitor.
The final gain stage consists of
an op- amp configured in an
inverting configuration and DC
biased at 2.27 V. The actual gain
of this gain stage is user
programmable with external
resistors R1 and R2 as shown in
Figure 17. The signal output at
Rx- out (pin 6) is buffered and
may be directly connected to
the demodulator or ADC, using
AC coupling if required.
Internal Protection and Sensing
The HCPL- 810J includes several
sensing and protection functions
to ensure robust operation
under wide ranging
environmental conditions.
The first feature is the V_CC2
Under Voltage Detection (UVD).
In the event of V_CC2 dropping to
a voltage less than 4 V, the
output status pin is switched to
a logic low state.
The next feature is the over-
temperature shutdown. This
particular feature protects the
line driver stage from over-
temperature stress. Should the
IC junction temperature reach a
level above 130°C, the line
driver circuit is shut down,
simultaneously the output of
Status (pin 5) is pulled to the
logic low state.
The final feature is load
detection function. The
powerline impedance is quite
unpredictable and varies not
just at different connection
points but is also time variant.
The HCPL- 810J includes a
current sense feature, which
may be utilized to feedback
information on the
instantaneous powerline load
condition. Should the peak
current reach a level greater
than 0.6 A_PP, the output of
Status pin is pulled to a logic
low state for the entire period
the peak current exceeds - 0.3 A,
as shown in Figure 21. Using
the period of the pulse together
with the known coupling
impedance, the actual powerline
load can be calculated. Table 2
shows the logic output of the
Status pin.
External Transient Voltage Protection
To protect the HCPL- 810J from
high voltage transients caused
by power surges and
disconnecting/connecting the
modem, it is necessary to add
an external 6.8 V bi- directional
transient voltage protector (as
component D1 shown in Figure
17).
Additional protection from
powerline voltage surges can be
achieved by adding an
appropriate Metal Oxide
Varistor (MOV) across the
powerline terminals after the
fuse.
Table 2. Status pin logic output.
Mode
Receiver Mode
Transmitter Mode
Normal V_CC2 < 4V Over-Temperature I_Tx-out < −0.3 A
High Low
-
-
High Low
Low
Low (pulsed)
Tx-out (pin 15)
0.5 A/Div
I_th
2 µs/Div
tth
Status (pin 5)
2 V/Div
tth
Figure 21. Transmit output load detection.
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