RFM31 Datasheet, PDF (85/137 Pages) –

RFM31
Register 1Fh. Clock Recovery Gearshift Override
Bit
D7
D6
D5
D4
D3
Name
Reserved
rxready
crfast[2:0]
Type
R/W
R/W
R/W
Reset value = 00000011
D2
D1
D0
crslow[2:0]
R/W
Bit
Name
7
Reserved Reserved.
Function
Improves Receiver Noise Immunity when in Direct Mode.
It is recommended to set this bit after preamble is detected. When in FIFO
6
rxready
mode this bit should be set to ―0‖ since noise immunity is controlled
automatically.
5:3
crfast[2:0] Clock Recovery Fast Gearshift Value.
2:0
crslow[2:0] Clock Recovery Slow Gearshift Value.
The gear-shift register controls BCR loop gain. Before the preamble is detected, BCR loop gain is as follows:
crgain
BCRLoopGain = _2crfast
Once the preamble is detected, internal state machine automatically shift BCR loop gain to the following:
crgain
BCRLoopGain = _2crslow
crfast = 3‘b000 and crslow = 3‘b101 are recommended for most applications. The value of ―crslow‖ should be
greater than ―crfast‖.
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