RFM31 Datasheet, PDF (41/137 Pages) –

RFM31
8. Auxiliary Functions
8.1. Smart Reset
The RFM31 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a
classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable
reset signal in any circumstances. Reset will be initiated if any of the following conditions occur:
Initial power on, when VDD starts from 0V: reset is active till VDD reaches VRR (see table);
When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR again;
A software reset via ―Register 08h. Operating Mode and Function Control 2,‖: reset is active for time.TSWRST
On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit:
Figure 17. POR Glitch Parameters
Table 21. POR Parameters
Parameter
Symbol
Comment
Min
Typ Max Units
Release Reset Voltage
VRR
0.85
1.3 1.75 V
Power-On VDD Slope
SVDD
tested VDD slope region
0.03
300 V/ms 0.03
Low VDD Limit
VLD
VLD<VRR is guaranteed
0.7
1
1.3
V
Software Reset Pulse
TSWRST
50
470 us
Threshold Voltage
VTSD
0.4
V
Reference Slope
k
0.2
V/ms
VDD Glitch Reset Pulse
Also occurs after SDN, and
TP
5
initial power on
15 40 ms
The reset will initialize all registers to their default values. The reset signal is also available for output and use by
the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on
GPIO_1.
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