RFM31 Datasheet, PDF (72/137 Pages) –

RFM31
Register 0Ah. Microcontroller Output Clock
Bit
Name
Type
D7
D6
Reserved
R
D5
D4
clkt[1:0]
R/w
Reset value = xx000110
D3
enlfc
R/w
D2
D1
D0
mclk[2:0]
R/w
Bit
Name
Function
7:6
Reserved Reserved.
Clock Tail.
If enlfc = 0 then it can be useful to provide a few extra cycles for the
microcontroller to complete its operation. Setting the clkt[1:0] register will
provide the addition cycles of the clock before it shuts off.
5:4
clkt[1:0]
00: 0 cycle
01: 128 cycles
10: 256 cycles
11: 512 cycles
Enable Low Frequency Clock.
When enlfc = 1 and the module is in Sleep mode then the 32.768 kHz clock will
be provided to the microcontroller no matter what the selection of mclk[2:0] is.
3
enlfc
For example if mclk[2:0] = ‗000‘, 30 MHz will be available through the GPIO to
output to the microcontroller in all Idle or TX states. When the module is
commanded to Sleep mode the 30 MHz clock will become 32.768 kHz.
Microcontroller Clock.
Different clock frequencies may be selected for configurable GPIO clock
output. All clock frequencies are created by dividing the XTAL except for the 32
kHz clock which comes directly from the 32 kHz RC Oscillator. The mclk[2:0]
setting is only valid when xton = 1 except the 111.
000: 30 MHz
2:0
mclk[2:0] 001: 15 MHz
010: 10 MHz
011: 4 MHz
100: 3 MHz
101: 2 MHz
110: 1 MHz
111: 32.768 kHz
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