HD66750 Datasheet, PDF (87/96 Pages) Hitachi Semiconductor – 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions

HD66750/1
80-system Bus Interface Timing Characteristics
(Vcc = 1.8 to 2.4 V)
Item
Symbol Min
Bus cycle time
Write t_CYCW 600
Read t_CYCR
800
Write low-level pulse width
PW_LW 120
Read low-level pulse width
PW_LR 350
Write high-level pulse width
PW_HW 300
Read high-level pulse width
PW_HR 300
Write/Read rise/fall time
t_WRr , _WRf Ñ
Setup time (RS to CS*, WR*, RD*)
t _AS
50
Address hold time
t _AH
20
Write data setup time
t _DSW
60
Write data hold time
t_H
20
Read data delay time
t _DDR
Ñ
Read data hold time
t _DHR
5
Typ Max Unit Test Condition
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
25
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
300 ns
Figure 63
Ñ
Ñ
ns
Figure 63
(Vcc = 2.4 to 3.6 V)
Item
Symbol Min
Bus cycle time
Write t_CYCW 380
Read t_CYCR
500
Write low-level pulse width
PW_LW 70
Read low-level pulse width
PW_LR 250
Write high-level pulse width
PW_HW 150
Read high-level pulse width
PW_HR 150
Write/Read rise/fall time
t Ñ _{WRr, WRf}
Setup time (RS to CS*, WR*, RD*)
t _AS
50
Address hold time
t _AH
20
Write data setup time
t _DSW
60
Write data hold time
t_H
20
Read data delay time
t _DDR
Ñ
Read data hold time
t _DHR
5
Typ Max Unit Test Condition
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
25
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
Ñ
ns
Figure 63
Ñ
200 ns
Figure 63
Ñ
Ñ
ns
Figure 63
Reset Timing Characteristics (V_CC = 1.8 to 3.6 V)
Item
Reset low-level width
Symbol Min
Typ
t _RES
1
Ñ
Max
Unit
Ñ
ms
Test Condition
Figure 64
87