HD66750 Datasheet, PDF (40/96 Pages) Hitachi Semiconductor – 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions

HD66750/1
Parallel Data Transfer
16-bit Bus Interface
Setting the IM2–0 (interface mode) to the GND/GND level allows 68-system E-clock-synchronized 16-bit
parallel data transfer. Setting the IM1/0 to the Vcc/GND level allows 80-system 16-bit parallel data
transfer. When the number of buses or the mounting area is limited, use an 8-bit bus interface.
CSn*
A1
H8/2245 HWR*
(RD*)
D15–D0
16
CS*
RS
WR* ^HD66750/1
(RD*)
DB15–DB0
Figure 22 Interface to 16-bit Microcomputer
8-bit Bus Interface
Setting the IM1/0 (interface mode) to the GND/Vcc level allows 68-system E-clock-synchronized 8-bit
parallel data transfer using pins DB15–DB8. Setting the IM1/0 to the Vcc/Vcc level allows 80-system 8-
bit parallel data transfer. The 16-bit index register, instructions and RAM data are divided into eight
upper/lower bits and the transfer starts from the upper eight bits. Fix unused pins DB7–DB0 to the Vcc or
GND level.
CSn*
A1
H8/2245 HWR*
(RD*)
D15–D8
8
8
GND
CS*
RS
WR* ^HD66750/1
(RD*)
DB15–DB8
DB7–0
Figure 23 Interface to 8-bit Microcomputer
Note:
Transfer synchronization function for an 8-bit bus interface
The HD66750/1 supports the transfer synchronization function which resets the upper/lower
counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer
mismatch between the eight upper and lower bits can be corrected by a reset triggered by
consecutively writing a 00H instruction four times. The next transfer starts from the upper eight
bits. Executing synchronization function periodically can recover any runaway in the display
system.
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