HD66750 Datasheet, PDF (37/96 Pages) Hitachi Semiconductor – 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions

HD66750/1
Read Data from CGRAM
RD15-0 : Read 16-bit data from the CGRAM. When the data is read to the microcomputer, the first-word
read immediately after the CGRAM address setting is latched from the CGRAM to the internal read-data
latch. The data on the data bus (DB15Ð0) becomes invalid and the second-word read is normal.
When bit processing, such as a logical operation, is performed within the HD66750/1, only one read can be
processed since the latched data in the first word is used.
R/W RS DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 ^{RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD}
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 20 Read Data from CGRAM Instruction
Sets the I/D and AM1Ð0 bits
Address: N set
First word
Dummy read (invalid data)
CGRAM -> Read-data latch
Sets the I/D and AM1Ð0 bits
Address: N set
First word
Dummy read (invalid data)
CGRAM -> Read-data latch
Second word
Read (data of address n)
Read-data latch -> DB15Ð0
Second word
Read (data of address n)
DB15Ð0 -> CGRAM
Address: M set
First word
Dummy read (invalid data)
CGRAM -> Read-data latch
Automatic address update: M + α
First word
Dummy read (invalid data)
CGRAM -> Read-data latch
Second word
Read (data of address)
Read-data latch -> DB15Ð0
Second word
Write (data of address n)
DB15Ð0 -> CGRAM
i) Data read to the microcomputer
ii) Logical operation processing in the HD66750/1
Figure 21 CGRAM Read Sequence
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