HD66750 Datasheet, PDF (26/96 Pages) Hitachi Semiconductor – 128 x 128-dot Graphics LCD Controller/Driver with Four-grayscale Functions

HD66750/1
Table 8
BS2
0
0
0
0
1
1
1
1
BS Bits and LCD Drive Bias Value
BS1
BS0
LCD Drive Bias Value
0
0
1/11 bias drive
0
1
1/10 bias drive
1
0
1/9 bias drive
1
1
1/8 bias drive
0
0
1/7 bias drive
0
1
1/6 bias drive
1
0
1/5 bias drive
1
1
1/4 bias drive
Table 9
BT1
0
0
1
1
BT Bits and Output Level
BT0
V5OUT Output Level
0
Two-times boost
1
Five-times boost
0
Six-times boost
1
Seven-times boost
Table 10 DC Bits and Operating Clock Frequency
DC1
0
0
1
1
DC0
0
1
0
1
Operating Clock Frequency in the Booster
32-divided clock
16-divided clock
8-divided clock
4-divided clock
Table 11 AP Bits and Amount of Fixed Current
AP1
AP0
Amount of Fixed Current in the Operational Amplifier
0
0
Operational amplifier and booster do not operate.
0
1
Small
1
0
Middle
1
1
Large
SLP: When SLP = 1, the HD66750/1 enters the sleep mode, where the internal display operations are
halted except for the R-C oscillator, thus reducing current consumption. For details, see the Sleep Mode
section. Only the following instructions can be executed during the sleep mode.
Power control (BS2Ð0, BT1Ð0, DC1Ð0, AP1Ð0, SLP, and STB bits)
During the sleep mode, the other CGRAM data and instructions cannot be updated although they are
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