HD155121F Datasheet, PDF (8/57 Pages) Hitachi Semiconductor – RF Transceiver IC for GSM and PCN Dual band cellular systems

HD155121F
Functional Operation
The HD155121F has been designed from system stand point and incorporated a large number of the circuit
blocks necessary in the design of a digital cellular handset.
Receiver Operation
The HD155121F incorporates two LNA bias circuits for external RF transistors, whose NF and power gain
can be better selected.
This circuit amplifies the RF signal after selection by the antenna filter before the signal enters the first
mixer section. The RF signal is combined with a local oscillator (LO) signal to generate a wanted first IF
signal in the 130 - 300 MHz range. The first mixer circuit uses a double-balanced Gilbert cell architecture,
which has open collector differential outputs. If, at 225 MHz, a 800 Ω LC load is connected to the mixer’s
outputs then a SSB NF of 9.0 dB (GSM), 9.1 dB (PCN) with a gain of 9.5 dB (GSM), 8.5 dB (PCN) is
realizable. The corresponding input compression point is –10.5 dBm (GSM), –12.5 dBm (PCN), which
allows the device to be used within a GSM and EGSM and PCN system.
A filter is used after the first mixer to provide image rejection and the conditioned signal is then passed
through an intermediate amplifier, before being down converted to a second IF in the range of 26 - 60
MHz.
The second mixer can generate a 45 MHz second IF, if a 270 MHz second local signal is used. The second
mixer also uses the Gilbert cell architecture, but with internal resistive differential outputs of 300 Ω. If
amplifier and second mixer has a SSB NF of 6.0 dB, a power gain of 13 dB and a input compression point
of –22 dBm. In order to improve the blocking characteristics of the device an external LC resonator across
the differential outputs of the second mixer is recommended.
First mixer and second mixer can switch the power gain. Switching gain step of first mixer is 12 dB, and
such step of second mixer is 16 dB.
The signal is then passed to the PGA circuit, which has a dynamic range of more than 80 dB (–42 dB - +56
dB typ.) and is controlled by digital serial data, which is generated by the microprocessor. This gain step is
2 dB.
The signal is then down converted by a demodulator to I and Q. Internal divider circuits convert the IFLO
signal to the same frequency as the second IF before passing this local signal through a phase splitter /
shifter in order to generate the in phase and quadrature phase IQ components. The phase accuracy of the
IQ demodulator is less than +/–1 degree and the amplitude mismatch is less than +/–0.5 dB. In order to
accommodate different baseband interfaces the HD155121F IQ differential outputs have a voltage swing of
1.6 Vpp and DC offset of less than +/–60 mV. Within each output stage a second order Butterworth filter
(fc = 210 kHz) is used to improve the blocking performance of the device.
In order to allow flexibility in circuit implementation the HD155121F can configured to use either a single-
ended or balanced external circuitry and components.
8