HD155121F Datasheet, PDF (53/57 Pages) Hitachi Semiconductor – RF Transceiver IC for GSM and PCN Dual band cellular systems

HD155121F
Phase detector
R3
VCO
C2
C1
C3
R2
Figure A-1 Loop Filter Circuit of OPLL
The following equations provide a good starting point for the design of the OPLL.
Let:
f₀ = Closed loop unity gain frequency (Hz) (Closed loop bandwidth)
f_n = f₀ / 2 = Closed loop resonant frequency (Hz)
ω_n = 2π ⋅ f_n
k _v = VCO gain (Hz / V)
k _vr = 2 ⋅ π ⋅ k _v (rad / V sec)
k_d = Peak phase dotector current = 1.2 (mA) in GSM mod e (at RICURAD = 22 kΩ)
k_dr = Phase det ector gain = ( 2 ⋅ k_d ) / π = 1.7 / π (mA / rad) (at RICURAD = 22 kΩ)
ξ = DampingFactor ≅ 0.9
Then:
C2 = k _vr ⋅ k_dr / ω_n2
R2 = 2 ⋅ ξ ⋅ 1 /(k_v ⋅ k_d ⋅ C2) = (2 ⋅ ξ) /(ω_n ⋅ C2)
C1 = C2 / 15
R3 ⋅ C3 ≅ 1 /(10 ⋅ ω_n )
Note that many VCO modules have up to 100 pF capacitance on the control line. This can be very
significant when designing high bandwidth loops.
The phase detector peak output current is centered around 1.2 mA which is set by an 22 kΩ resistor
RICURAD on pin 12.
For example, the f₀ = 1.2 MHz loop filter using the VCO of k_v = 30 MHz / V (GSM) should be designed in
the following method.
Let:
f₀ = 1.2 (MHz) = 1.2 × 10⁶ (Hz)
f_n = f₀ / 2 = 600 (kHz) = 6 × 10⁵ (Hz)
ω_n = 2π ⋅ f_n = 2π ⋅ 6 × 10⁵ (rad / sec)
k_v = 30 (MHz / V) = 30 × 10⁶ (Hz / V)
k_vr = 2π ⋅ k_v = 2π × 30 × 10⁶ (rad / V sec)
k_d = 1.2 (mA) (at RICURAD = 22 kΩ)
k_dr = 1.7 / π (mA / rad) = 1.7 × 10^−3) / π (A / rad) (at RICURAD = 22 kΩ)
ξ = Damping Factor ≅ 0.9
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