HD155121F Datasheet, PDF (54/57 Pages) Hitachi Semiconductor – RF Transceiver IC for GSM and PCN Dual band cellular systems

HD155121F
Then:
C2
=
k _vr
⋅ k _dr
/
ω
2
n
=
2 × 30 × 10⁶ × 1.7 × 10^−3
(2π × 6 × 10⁵ )²
= 7.2 × 10^−9
= 7.2 nF
R2 = (2 ⋅ ξ) / (ω_n ⋅ C2) =
2 × 0.9
2π × 6 × 10⁵ × 7.2 × 10^−9
= 66 Ω
C1 = C2 / 15 = (7.2 × 10^−9 ) / 15 = 480 pF
R3 ⋅ C3
≅ 1/(10 ⋅ ω_n )
=
2π
1
× 6 × 10⁶
When the VCO modules have 33 pF capacitance on the control line, C3 is 33 pF.
C3 = 33 pF
R3 = 804 Ω
The result of the calculations for the PLL loop characteristic,based on the following block diagram (figure
A-2), is showed in figure A-3 and figure A-4. The offset PLL will be stable if the component values shown
are used.
k_dr
Input phase _Phase
+ detector
−
C2
7.2n
C1
480p
VCO module
k_vr/S
R3
VCO
804
C3
33p
R2
66
Output phase
Unit: R : Ω
C:F
k_vr = 2π ⋅ k_v = 2π × 30 × 10⁶ (rad / Vsec)
k_dr = (1.7 × 10^−3) / π (A / rad)
VCO module example
GSM: MURATA MQE9P7-897
C3 = 33pF
k_v = 30MHz/V
PCN: MURATA MQE9P7-1747
C3 = 22pF
k_v = 47MHz/V
Figure A-2 Block Diagram for OPLL Simulation
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